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Existing solutions
High voltage circuit for implementing the method is
not much. Can be used to achieve high tolerance transistor technical solutions
( such as multi- gate oxide layer ) , but at the cost of the production process
more expensive , have to add additional baseline CMOS process masks and
processing steps , so this solution is not ideal . In addition, to reliably
increase the pressure tolerance, can be used using only the standard baseline
transistor ( using a thin / thick oxide layer device ) circuit arrangement . In
the second method , the device stack or series are the most common examples of
the cathode . However , the complexity and performance of the RF has serious
limitations , especially when used in tandem cathode ( or stacked ) to increase
the number of devices to two or three or more . Another way to achieve a high
voltage circuit as described herein, the baseline CMOS technology drain-
extended field effect transistor (EDMOS) to achieve.
New solutions
Drain extension device is based on intelligent
routing technology , which benefited from the ACTIVE ( silicon ), STI ( oxide
layer ) and GATE ( polysilicon ) region can be achieved in a very fine size ,
and can no additional cost conditions, using the baseline deep submicron CMOS
technology to achieve two kinds of high-voltage PMOS and NMOS transistors
tolerance . Although the process with the use of standard transistors compared
to those of the RF device performance is virtually EDMOS low, but due to
elimination of HV equivalent circuit associated with other important loss
mechanism ( such as a cathode in series ) that are still in the high voltage
circuit to achieve a high overall performance.
Therefore, this high-voltage CMOS driver of the
topology EDMOS devices used to prevent the device stack. RF CMOS driver uses
the device through the thin oxide layer EDMOS baseline 65nm low standby power
CMOS process, and requires no additional mask steps or processes. For PMOS and
NMOS , these devices were measured fT over 30GHz and 50GHz, their breakdown
voltage limit is 12V. Unprecedented high-speed CMOS driver delivers up to
3.6GHz 8Vpp output swing , and thus be able to be like GaN this offer based on
wide bandgap SMPA drive .
Figure 1 herein a schematic structural view of the
driver . The output stage includes an
pure sine wave power inverter
-based EDMOS . EDMOS standard
transistor device can be low- speed direct-drive , thereby simplifying the output
stage with other digital and analog CMOS circuit integrated on a single chip .
Each EDMOS transistors are CMOS inverters via three -level implementation of
the tapered buffer ( buffer in Figure 1 A and B) provide drivers . Two buffers
with different DC levels to ensure that each CMOS inverter can be in a 1.2V
voltage ( subject to technical constraints, namely VDD1-VSS1 = VDD0-VSS0 =
1.2V) stable operation. In order to use a different supply voltage and allow
the same AC operation , two identical buffers constructed and built in a
separate Deep N-Well (DNW) layer. Driver output swing by the VDD1-VSS0
decisions are free to choose the device does not exceed the maximum breakdown
voltage EDMOS any value , and the internal operation of the driver remain unchanged.
DC level shift circuit separable each buffer input signal.
